Non-volatile memory cells having a floating gate or a trapping charge layer for the storage of charges thereon are well known in the art. Referring to FIG. 1 there is shown a cross-sectional view of a non-volatile memory cell 10 (split gate source side injection hot electron programming cell) of the prior art. The memory cell 10 comprises a single crystalline substrate 12, of a first conductivity type, such as P type. At or near a surface of the substrate 12 is a first region 14 of a second conductivity type, such as N type. Spaced apart from the first region 14 is a second region 16 also of the second conductivity type. Between the first region 14 and the second region 16 is a channel region 18. A word line 20, made of polysilicon is positioned over a first portion of the channel region 18. The word line 20 is spaced apart from the channel region 18 by an insulating layer 22, such as silicon (di)oxide. Immediately adjacent to and spaced apart from the word line 20 is a floating gate 24, which is also made of polysilicon, and is positioned over another portion of the channel region 18. The floating gate 24 is separated from the channel region 18 by another insulating layer 30, typically also of silicon (di)oxide. A coupling gate 26, also made of polysilicon is positioned over the floating gate 24 and is insulated therefrom by another insulating layer 32. On another side of the floating gate 24, and spaced apart therefrom, is an erase gate 28, also made of polysilicon. The erase gate 28 is positioned over the second region 16 and is insulated therefrom. The erase gate 28 is adjacent to and spaced apart from the coupling gate 26. The erase gate 28 can have a slight overhang over the floating gate 24. In the operation of the memory cell 10, charge stored on the floating gate 24 controls the flow of current between the first region 14 and the second region 16. Where the floating gate 24 is negatively charged thereon, the memory cell is programmed. Where the floating gate 24 is positively charged thereon, the memory cell is erased. The memory cell 10 is fully disclosed in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein in its entirety by reference.
The memory cell 10 operates as follows. During the erase operation, when electrons are removed from the floating gate 24, a high positive voltage, e.g. 8-11V, is applied to the erase gate 28. A negative voltage, e.g., −6 to −8V or ground voltage can be applied to the coupling gate 26 and/or the word line 20. Electrons are transferred from the floating gate 24 to the erase gate 28 by Fowler-Nordheim tunneling through the insulating layer between the floating gate 24 and the erase gate 28. In particular, the floating gate 24 may be formed with a sharp tip facing the erase gate 28, thereby facilitating said tunneling of electrons. During the erase operation, the high positive voltage is supplied from a charge pump 52 (shown in FIG. 2). Typically, because the erase operation involves only the removal of electrons from the floating gate 24, the charge pump 52 need not supply a large current (typically in nanoampere range).
Thereafter, the memory cell 10 can be programmed. During the programming operation, when electrons are injected to the floating gate 24 through hot-electron injection with the portion of the channel 18 under the floating gate 24 in inversion, a first positive voltage, e.g. 1V to 2V, in the shape of a pulse is applied to the word line 20 causing the portion of the channel region 18 under the word line 20 to be conductive. A second positive voltage, e.g, 8V to 10V, also in the shape of a pulse, is applied to the coupling gate 26, to utilize high coupling ratio between coupling gate 26 and floating gate 24 to maximize the voltage coupling to the floating gate 24. A third positive voltage, e.g, 3V to 6V, also in the shape of a pulse, is applied to the erase gate 28, to utilize coupling ratio between erase gate 28 and floating gate 24 to maximize the voltage coupling to the floating gate 24. A high voltage differential, e.g, 4V to 7V, also in the shape of a pulse, is applied between the first region 14 and the second region 16, to provide generation of hot electrons in the channel 18. Thus, during the programming operation a current (typically in microamperes) flows between the first region 14 and the second region 16 which must be supplied from the charge pump 52.
During the read operation, a first positive voltage, e.g., 1V to 3V, is applied to the word line 20 to turn on the portion of the channel region 18 beneath the word line 20. A second positive voltage, e.g, 0V to 4V, is applied to the coupling gate 26. A third voltage, e.g, 0V to 3V, is applied to the erase gate 28. A voltage differential, e.g, 0.5V to 2V, is applied to the first region 14 and the second region 16. If the floating gate 24 were programmed, i.e. the floating gate 24 stores electrons, then the second positive voltage applied to the coupling gate 26 and the third voltage applied to the erase gate 28 is not able to overcome the negative electrons stored on the floating gate 24 and the portion of the channel region 18 beneath the floating gate 24 remains non-conductive. Thus, no current or a negligibly small amount of current would flow between the first region 14 and the second region 16. However, if the floating gate 24 were not programmed, i.e. the floating gate 24 remains neutral or positively charged, then the second positive voltage applied to the coupling gate 26 and the third voltage applied to the erase gate 28 is able to cause the portion of the channel region 18 beneath the floating gate 24 to be conductive. Thus, a current would flow between the first region 14 and the second region 16.
As is well known, memory cells 10 are typically formed in an array, having a plurality of rows and columns of memory cells 10, on a semiconductor wafer. Referring to FIG. 2 there is shown a block level diagram of a memory device 50 of the prior art with an array 60 of memory cells 10. FIG. 3 is a more detailed diagram of the array 60 shown in FIG. 2. The array 60 comprises a plurality of subarrays 62 (a-d), with a plurality of memory cells, such as memory cells 10 arranged in a plurality of rows and columns. Associated with each row of memory cells 10 spanning across the subarrays 62a, 62b, 62e and 62d is a row decoder (aka xdec, also wordline decoder) 64. Associated with columns of memory cells 10 in each subarray, e.g. subarray 62a are sense amplifiers 70a and 70b. A column (bitline) decoder (ymux, not shown) is used to select (multiplex, decode) columns of memory cells into sense amplifiers. From the sense amplifiers 70, the signals are supplied to an output register 72. In the embodiment shown in FIG. 3, each subarray 62 is multiplexed (i.e., decoded by a ymux, not shown) into two words with each word having 16 bits. In one embodiment in the subarray array 62, each row has 2048 memory cells, the first 1024 cells is multiplexed into a 1st word (to be programmed) and the second 1024 cells is multiplexed into a 2nd word (to be programmed).
During erase, a block or group of units (such as a number of bytes (with 8 bits to a byte)) of memory cells are erased at once. The erase operation places the plurality of bits into a state of “FF” (hex), or “11111111”. During programming, selected bits of a byte are programmed by injecting electrons onto the floating gate into the logical state of “0”. However, the charge pump 52 must be able to supply programming current as if all of the bits of a byte are to be programmed. Thus, the charge pump 52 must be designed with the ability to supply programming current as if all the bits of the byte were to be programmed to the state of “00” (hex), or “00000000”. Furthermore, to increase performance, a number of bytes are programmed simultaneously. This adds further burden on the charge pump 52 to provide a large programming current. Since a charge pump 52 capable of providing a large current requires a large amount of real estate on the silicon die, a larger charge pump 52 takes up more silicon real estate. Thus, it is one objective of the present invention to reduce the size of the charge pump 52.
Finally, parity bits are well known in the art. A parity bit is a bit associated with a plurality of bits (such as a byte) in which the parity bit is programmed to a state representing an error check on the data stored in the byte. However, typically parity bits have been used with volatile memory cells, and have been used only for error correction.